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| 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold November 1999 Revised June 2005 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold General Description The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The VCXH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16244 is designed for low voltage (1.2V to 3.6V) VCC applications with output capability up to 3.6V. The 74VCXH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.2V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminating the need for external pull-up/pull-down resistors s tPD 2.5 ns max for 3.0V to 3.6V VCC s Static Drive (IOH/IOL) r24 mA @ 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74VCXH16244G (Note 1)(Note 2) 74VCXH16244MTD (Note 2) Package Number BGA54A (Preliminary) MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: Ordering Code "G" indicates Tray. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbol (c) 2005 Fairchild Semiconductor Corporation DS500230 www.fairchildsemi.com 74VCXH16244 Connection Diagrams Pin Assignment for TSSOP Pin Descriptions Pin Names OEn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Bushold Inputs Outputs No Connect FBGA Pin Assignments 1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE4 4 OE2 NC VCC GND GND GND VCC NC OE3 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15 Truth Tables Inputs OE1 Pin Assignment for FBGA L L H Inputs OE2 L L H Inputs (Top Thru View) OE3 L L H Inputs OE4 L L H I12-I15 L H X I8-I11 L H X I4-I7 L H X I0-I3 L H X Outputs O0-O3 L H Z Outputs O4-O7 L H Z Outputs O8-O11 L H Z Outputs O12-O15 L H Z H HIGH Voltage Level L LOW Voltage Level X Immaterial (HIGH or LOW, inputs may not float) Z High Impedance www.fairchildsemi.com 2 74VCXH16244 Functional Description The 74VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. Logic Diagram 3 www.fairchildsemi.com 74VCXH16244 Absolute Maximum Ratings(Note 3) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 4) DC Input Diode Current (IIK) VI 0V DC Output Diode Current (IOK) VO 0V VO ! VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (I CC or GND) Storage Temperature Range (TSTG) 0.5V to 4.6V 0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA 50 mA r50 mA r100 mA 65qC to 150qC Recommended Operating Conditions (Note 5) Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC VCC VCC VCC VCC 3.0V to 3.6V 2.3V to 2.7V 1.65V to 2.3V 1.4V to 1.6V 1.2V 0.0V to VCC 0.0V to 3.6V 1.2V to 3.6V 0.3V to 3.6V Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V r24 mA r18 mA r6 mA r2 mA r100 PA 40qC to 85qC 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 1.2 VIL LOW Level Input Voltage 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 1.2 VOH HIGH Level Output Voltage IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH 2.0 1.6 0.65 x VCC 0.65 x VCC 0.65 x VCC 0.8 0.7 0.35 x VCC 0.35 x VCC 0.05 x VCC VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2.0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 VCC - 0.2 V V V Min Max Units 100 PA 12 mA 18 mA 24 mA 100 PA 6 mA 12 mA 18 mA 100 PA 6 mA 100 PA 2 mA 100 PA 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 1.2 www.fairchildsemi.com 4 74VCXH16244 DC Electrical Characteristics Symbol VOL Parameter LOW Level Output Voltage (Continued) VCC (V) IOL IOL IOL IOL IOL IOL IOL IOL IOL IOL IOL IOL 100 PA 12 mA 18 mA 24 mA 100 PA 12 mA 18 mA 100 PA 6 mA 100 PA 2 mA 100 PA V CC or GND 0.8V 2.0V 0.7V 1.6V 0.57V 1.07V 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 1.2 1.2 - 3.6 1.2 - 3.6 3.0 3.0 2.3 2.3 1.65 1.65 3.6 3.6 2.7 2.7 1.95 1.95 2.7 - 3.6 0 1.2 - 3.6 1.2 - 3.6 2.7 - 3.6 75.0 0.2 0.4 0.4 0.55 0.2 0.4 0.6 0.2 0.3 0.2 0.35 0.05 V Conditions Min Max Units II II(HOLD) Input Leakage Current Bushold Input Minimum Drive Hold Current Control Pins Data Pins 0 d VI d 3.6V VI VIN VIN VIN VIN VIN VIN r5.0 r5.0 75.0 45.0 PA PA 45.0 25.0 PA 25.0 450 II(OD) Bushold Input Over-Drive Current to Change State (Note 6) (Note 7) (Note 6) (Note 7) (Note 6) (Note 7) 450 300 300 200 PA 200 r10.0 10.0 20.0 IOZ IOFF ICC 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input 0 d VO d 3.6V VI VI VIH V IH or VIL V CC or GND VCC 0.6V 0 d (VO) d 3.6V VCC d (VO) d 3.6V (Note 8) PA PA PA PA PA r20.0 750 'ICC Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCXH16244 AC Electrical Characteristics Symbol tPHL tPLH CL tPZL tPZH CL tPLZ tPHZ CL tOSHL tOSLH Output to Output Skew (Note 10) CL Note 9: For CL (Note 9) Conditions VCC (V) 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 TA Parameter Propagation Delay CL 40qC to 85qC Max 2.5 3.0 6.0 12.0 30.0 3.5 4.1 8.2 16.4 41.0 3.5 3.8 6.8 13.6 34.0 0.5 0.5 0.75 1.5 1.5 Min 0.8 1.0 1.5 1.0 1.5 0.8 1.0 1.5 1.0 1.5 0.8 1.0 1.5 1.0 1.5 Units Figure Number Figures 1, 2 30 pF, RL 500: ns Figures 5, 6 Figures 1, 3, 4 ns Figures 5, 7, 8 Figures 1, 3, 4 ns Figures 5, 7, 8 15 pF, RL 30 pF, RL 2 k: 500: 1.5 r 0.1 1.2 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 Output Enable Time CL 15 pF, RL 30 pF, RL 2 k: 500: 1.5 r 0.1 1.2 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 Output Disable Time CL 15 pF, RL 30 pF, RL 2 k: 500: 1.5 r 0.1 1.2 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 CL ns 15 pF, RL 2 k: 1.5 r 0.1 1.2 50PF, add approximately 300 ps to the AC maximum specification. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP Parameter Quiet Output Dynamic Peak VOL CL 30 pF, VIH Conditions VCC, VIL 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL 30 pF, VIH VCC, VIL 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL 30 pF, VIH VCC, VIL 0V 1.8 2.5 3.3 TA 25qC 0.25 0.6 0.8 Typical Units V 0.25 0.6 0.8 1.5 1.9 2.2 V V Capacitance Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance VCC VI VI Conditions 1.8, 2.5V or 3.3V, VI 0V or VCC, VCC 0V or VCC, f 0V or VCC 1.8V, 2.5V or 3.3V TA 25qC 6.0 7.0 20.0 Typical Units pF pF pF 1.8V, 2.5V or 3.3V 10 MHz, VCC www.fairchildsemi.com 6 74VCXH16244 AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V) TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open 6V at VCC 3.3 r 0.3V; VCC x 2 at VCC 2.5 r 0.2V; 1.8V r 0.15V GND FIGURE 1. AC Test Circuit FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V 1.8V r 0.15V VCC/2 VCC/2 VOL 0.15V VOH 0.15V 7 www.fairchildsemi.com 74VCXH16244 AC Loading and Waveforms (VCC 1.5 r 0.1V to 1.2V) TEST tPLH, tPHL tPZL, tPLZ tPZH , tPHZ SWITCH Open VCC x 2 at VCC GND 1.5 r 0.1V FIGURE 5. AC Test Circuit FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 1.5V r 0.1V VCC/2 VCC/2 VOL 0.1V VOH 0.1V www.fairchildsemi.com 8 74VCXH16244 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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